Generate

PCB Generator

Describe the load board; ATE·IQ authors it against your spec — grounded in a cited library of real ATE load-board knowledge — then checks its own work and repairs its findings before you see the result.

Design-to-spec authoring

A load board is not a generic PCB — it exists to serve a test program. So the generator does not start from the prompt alone: it injects the project's test requirements as design context. A spec that forces 3 mA on an output pin, or measures supply current to microamp limits, changes what the board must contain — terminations, Kelvin sensing, decoupling — and the model sees those requirements before it places a single part.

What the model writes is tscircuit source — typed JSX that compiles to the same canonical circuit-json every other design in ATE·IQ uses. The output is a first-class design: it lands in the library with provenance llm, renders through the multi-sheet schematic engine, and runs through the full analysis hub like any imported board.

Grounded, not recalled

The model does not design from memory. Its authoring is grounded in a cited library of ATE load-board knowledge — form factors, decoupling, grounding, Kelvin sensing, probe heads, routing conventions — where every entry carries its source, and in a curated library of real parts.

That grounding holds through repair as well as first authoring: when a check flags a part, the correction is made against recorded part data — never against the model's own recollection of a datasheet.

Checked and repaired before you see it

Every run is checked and repaired before it is presented. The generator compiles its own output offline, holds it to the same standard the analysis hub applies to every board — the generator cannot pass a check the review page would fail — and repairs what the checks find.

The loop is bounded, not open-ended. A clean result costs nothing extra; a result that still carries findings after repair is presented with those findings attached — never silently shipped, and never polished until it merely looks clean.

Proven end to end

The demonstration load board began as exactly this kind of run: the 34-requirement spec in context, the cited ATE knowledge supplying the series-termination, ESD-protection, decoupling and Kelvin force/sense conventions, and the compiled result landing in the library as a normal design. Because generation targets the spec, the rest of the loop lines up — consistent by construction, never by luck — and the traceability dashboard traces every test onto the generated copper.

Generated load board rendered by the schematic engine — Fig. 1 — A generated design is a normal design: the demonstration board rendered by the same 5-sheet schematic engine every design gets.

Honest boundary The repair loop is bounded and its verdicts are the offline checks' verdicts. A design that still carries findings is shown to you with those findings — the generator never loops until something looks clean, and it never hides what the checks found.