How an engineer actually uses it

You bring what you already have. The pilot reads it the way an engineer would.

No new file format. No re-modelling your test plan in someone else's tool. Point ATE·IQ at the artefacts already on your engineer's laptop and the tester next door — the workbook open in Excel right now, the git repo where the team commits VBA, the IPC-2581 export your CAD tool already produces, the STDF lot the prober dropped last shift. The loop is short on purpose: author → validate → compile → measure → author, and an engineer sees the consequence of an edit within minutes.

Two ways to start: warm from an open .xlsm you want to extend, or cold from a spec + your team's reference repo — the pilot bootstraps a first compiling test program from nothing but those two inputs.

01Bring your stack— five inputs, one project context

Five things you already have. One project that knows about all of them.

AWorkbook

Your IG-XL .xlsm

Open it in Excel. The task pane appears in the sidebar, reads every sheet (TestInst filters which VBA is active), and persists the workbook as a first-class project artefact.

task pane · 1-click ingest
BCode

Your test-program git repo

Point doc-ingestion at GitHub, GitLab, Bitbucket, or any HTTPS git URL — encrypted PAT, no public-clone requirement. code-map indexes every file's imports, exports, language. Pull updates with one click.

git over HTTPS · AES-256 PATs
CHardware

Your IPC-2581 designs

Drop an .ipc export or point at a repo of them. Each one becomes a typed PCBDesign — components, nets, layers, all queryable. The pilot reuses prior designs by refdes.

IPC-2581 · KiCad XML
DProduction

Your STDF lots

Native V4 binary parser (no Python at runtime). .std or .std.gz. Yield by site, first-fail pareto, parametric Cp/Cpk, wafer-map clusters, limits-vs-spec drift.

STDF V4 native · .std + .std.gz
ERequirements

Your specs

Jama Connect API sync (server URL + credentials). PDF datasheets section-indexed. Citation chips deep-link to the requirement line — no copy-paste between tabs.

Jama Connect · PDF
Project context

All five inputs flow into the same scored project context. The curator picks the relevant slice per task — the pilot never re-asks where things live.

.xlsmworkbookgittest-program repo.ipcPCB design.stdSTDF lotspecJama / PDFprojectcontext
stored where
Local PostgreSQL today, bundled SQLite at .exe ship. Nothing leaves the engineer's bench.
re-ingest cost
Re-clone a repo: incremental, only changed files re-index. Re-ingest a workbook: atomic delete + insert in one transaction.
02Cold start — from spec to a compiling test program— bootstrap a new project from nothing

Drop a spec. Point at your team's existing test programs. Get back a draft .igxlProj that IGLinkCL compiles.

Most teams have two things when a new device tapes out: a spec and a folder of test programs from previous devices. ATE·IQ takes both — reading the spec for the contract (what to test, against what limits) and the reference repo for the convention (how your team names procedures, structures sheets, lays out Pin Maps). The output isn't a sketch — it's a first .igxlProj with every mandatory block, every required sheet, every VBT_*.bas module, ready for IGLinkCL.

  • Spec is the contract. Each Jama requirement (or section of a parsed PDF) becomes a TestRequirement row. The pilot emits one or more test instances per requirement and tags them with <cite kind="spec" id="<specId>#<reqId>"/> chips so traceability is built-in.
  • Reference repo is the style guide. The pilot reads your team's existing tfContinuity / tfIDDQ / tfScanChain patterns and reuses them — same procedure-name convention (tf*), same Pin Levels layout, same SiteDouble idioms, same logging via TheExec.Datalog.WriteComment.
  • The output compiles. The .igxlProj has all 17 mandatory top-level blocks (SubPrograms, IGSecureOptions, Jobs, WorkBooks, etc.), every DeviceJob cross-reference (Subprogram: SheetName form), Windows backslashes in every Source path. Locked in by a regression test against a real working reference programme.
  • Validated before you see it. The cross-sheet validator runs between LLM output and storage — 8 rules across Flow / TestInst / Limits / Binning / Pin Levels. Failures land in the run's Validation tab; the pilot fixes the obvious ones in its second pass without re-prompting.
  • Traceable from day one. Every test instance carries a citation chip pointing at the spec line that justifies it. When QA asks "why does this device test this", the answer is one click away.
Cold-start flow
spec
REQ-001 · VDDPLL continuity · ≤500 mV
REQ-002 · IDDQ typical · ≤12 µA @ 25 °C
REQ-003 · Scan chain integrity · all sites
… 47 more
Jama · PDF
reference repo
pmic-rev1 / · 38 .bas modules
dac-rev2 / · 41 .bas modules
scan-ctrl / · 22 .bas modules
… 5 more devices
github · gitlab · bitbucket
draft test program
compiles
ATEIQ.igxlProj
Flow.txt
TestInst.txt
Limits.txt
Binning.txt
Levels_CONT.txt
Levels_VT.txt
VBT_TI_continuity.bas
VBT_TI_iddq.bas
VBT_TI_scanchain.bas
cross-sheet-validation.json
Reviewer's first click: open the Validation tab. 8 rules passed, 0 failures. Move to the diff.
03The curator scores what's relevant— and you see why

Per-task scoring. Transparent hits. You can toggle what the pilot reads.

Type a task in plain English. The context curator scores every CodeFile, PCBDesign, TestRequirement, and STDF lot in the project. Header tokens count 10×, body 1×, part-name matches +10 each (capped +30), recency decay −5/year (capped −15). Every score is visible — no "trust the LLM" magic.

The pilot only reads the items above the cut. You see exactly which files / designs / specs / lots will land in its context window before you send. Toggle a noisy item off; bring a borderline item in; hit Use 6 items in chat → to hand the selection over.

  • Per-item explanation — "why" field lists matching keywords. No black box.
  • Dependency awareness — if a scored module imports another, the dependency comes along. Marked via X.
  • Cross-surface — the same curator powers the standalone IDE pilot and the Excel task pane chat. One scoring algorithm, one project context.
context curator · pmic-rev3task: generate VDDPLL continuity
des
lm95231-evb-rev1
lm95231 ×3 · continuity ×2
96
spe
DS-LM95231 §6.2
VDDPLL ×2 · settle ×1
88
she
TestInst
tfContinuity ×4
74
vba
VBT_TI_continuity.basvia TestInst
tfContinuity ×6
71
cod
vbt-handlers.bas
Datalog ×2
63
lot
MXXXXXSC2E9921
VDDPLL ×1
41
cod
VBT_legacy_v1.bas
continuity ×1
28
5 of 7 included · est. 12.4K tokens
04Author with citations— every line points at its source

The pilot reuses what works, cites what it borrows, and shows you the delta.

Reuse-aware by design. When a prior design fits, the pilot doesn't re-invent — it copies forward with refdes preserved, then emits a delta block showing exactly what changed and what was reused verbatim. Reviewers can sign off on a small diff instead of auditing a regenerated file from scratch.

  • Citation chips render inline in prose — design / spec / part. Design chips link to /pcb/<id>; spec chips deep-link via <specId>#<reqId>; part chips point at the reference library.
  • Reasoning collapsibles — the LLM can emit a fenced reasoning block; the UI renders it as a closed-by-default <details> with "Reasoning · N steps".
  • Tool-call cards — when the pilot needs a chart from the STDF lot or a fresh requirement from Jama, it emits a fenced tool block with the call spelled out. Apply / Reject in-place.
pilot
▸ Reasoning · 3 steps
Reusing the continuity pattern from lm95231-evb-rev1 with the VDDPLL pin pair from DS-LM95231 §6.2. Tdelay 25 µs matches the rail's settle envelope; pin map already wires VDDPLL to DUT_VDDPLL.
VBT_TI_continuity.bas · +18 lines
Public Sub tfVDDPLL_Cont()
  TheHdw.DCVI.Pins("DUT_VDDPLL").Voltage = 1.8
  TheHdw.Wait 0.000025
  Dim sdRead As New SiteDouble
  sdRead = TheHdw.DCVI.Pins("DUT_VDDPLL") _
    .Meter.Read(tlStrobe)
  TheExec.DataManager.DataAcrossSites = sdRead
End Sub
Delta vs reused source
+ TestInst · tfVDDPLL_Cont
+ Limits · TNum 100 / bin 1
~ Levels_CONT · VDDPLL Tdelay 25 µs
tfContinuity proc · 0 line changes
05Validated before the reviewer sees it— three gates, on every generation

Thirty-one rules and a real IG-Link compile, between the pilot and your inbox.

AVBA quality
23 rules

R01–R23, dev/prod profiles. Option Explicit, OERN, GoTo, blocking timing, SendKeys, float equality, per-pin loops, ActiveSites enumeration outside report formatting, Hungarian-prefix mismatch, missing PassFail writes. Excel class modules skipped — only standard .bas modules analysed.

BCross-sheet validator
8 rules

Arg-ceiling (Arg ≥ 60 unusual), opcode allowlist, Flow → TestInst/Limits/Binning resolution, TestInst sheet-ref resolution (Pin Levels / Time Sets / Edge Sets / MST / Overlay), Pin Levels Tdelay sanity (negative + >1s unit confusion), tf* procedure-prefix convention.

CIG-Link CLI
exit 0 required

The generation pipeline runs IGLinkCL.exe against the draft .igxlProj. Compile log + every artefact (project / sheet / vba / output / log) becomes a downloadable run artefact. Cross-sheet result lands as cross-sheet-validation.json — advisory, never blocks compile.

/runs/[id]·a run artefact, viewable in-app
Artifacts tab
9 files grouped by kind — project / sheet / vba / output / log. Click-through download. Schema-validated names.
Validation tab
Cross-sheet result inline. Failures collapsible by rule. Pass-counts per rule. No JSON download needed.
Logs tab
IG-Link compile log, generation-runner log. Errored compiles surface the file + line, not just a stack trace.
06The loop closes— measure feeds back into author

Tests that ran badly become prompts for the pilot. Within minutes, not days.

When the STDF parser flags a test as a first-failure killer (the one that first kills each die — distinct from "top failing tests") or as a Cp/Cpk outlier with ≥ 2σ of spec headroom, the pilot reads the lot data alongside the test instance and proposes a targeted edit. The cross-sheet validator then catches any mismatch before the next compile.

The loop is short on purpose: author → validate → compile → measure → author. An engineer sees the consequence of an edit within minutes — not the next morning, not the next shift.

  • Yield by site with site→socket overlay. Flag the outlier socket without spelunking.
  • First-failure pareto — the top entry is the highest-leverage fix, by definition.
  • Limit-drift — tests ≥ 2σ inside the spec window flagged as relaxCandidate; σ-headroom quoted in the pilot's recommendation.
  • Cross-lot correlate — single test, multiple lots; trend detection over time.
Six surfaces, one loop01Ingest02Curate03Author04Validate05Compile06MeasureSTDF feedback

Forward path solid · feedback path dashed

07A 30-day pilot you can scope— concrete deltas, not vibes

First IG-Link draft compiled in week 1. Measurable delta by week 4.

Week 1

Stand-up

Install the .exe. Sideload the task pane manifest. Connect your test-program git repo with an encrypted PAT. Drop one .xlsm, one IPC-2581 export, one STDF lot. Pilot answers your first question with workbook + repo context.

Outputs
  • 1 project · 1 repo · 1 .xlsm · 1 lot ingested
  • First citation chip in chat
Week 2

First draft

Pilot generates a new test instance from an existing one. Cross-sheet validator runs. IG-Link compiles. Engineer reviews the delta block against the current workbook — not a regenerated file.

Outputs
  • 1 IG-Link compile exit 0
  • 1 reuse-aware delta reviewed
Week 3

Measure

Drop a real STDF lot from your tester. Pilot surfaces first-fail pareto + limit-drift candidates. You decide which to act on. STDF feedback loop runs end-to-end.

Outputs
  • 1 first-fail pareto generated
  • 1 σ-quoted relax recommendation
Week 4

Plan delta

Side-by-side: original test plan vs. ATE·IQ-assisted plan. Concrete delta in test-time, first-fail leverage, or new test coverage. Quote follows from the measured numbers — not from a marketing claim.

Outputs
  • 1 measured delta document
  • Pricing conversation