Product

Four intelligences, one tool — all wired to the same context.

Every surface reads from the same project context (workbook + repo + spec + designs + STDF lots). No swivel-chair between tools, no "refresh and try again".

01Pilot chatThe primary AI surface

An AI co-engineer that sees your whole project — and tells you what it's using.

Type a task in plain English. The context curator scores every file, design, spec, and STDF lot in the project by relevance — transparent scoring you can see and toggle. The pilot reads what an engineer would open, no more, no less.

Output is cited end-to-end. Reuse a prior design? <cite kind="design"/> chip links to /pcb/<id>. Quote a spec? <cite kind="spec"/> deep-links to the requirement. Touch a part? <cite kind="part"/> points at the parts library.

  • Reasoning collapsibles — the LLM can emit a fenced reasoning block; the UI renders it as a closed-by-default <details> with "Reasoning · N steps" summary.
  • Context curator UI — see every scored item before you send. Toggle items in/out. Hand off the selection to the pilot.
  • Workbook + spec aware — the open Excel workbook is ingested as project context; Jama Connect specs + PDF datasheets are section-indexed and citation-ready.
  • Reuse-aware delta — when a prior design fits, the pilot reuses it and surfaces the diff. Refdes preserved, parts list cited, additions explicit.
  • Live generation pipeline — curate → draft sheets → draft VBA → compile → verify, status visible per stage in the run viewer.
design chipspec chippart chipworkbook contextreuse-aware
pilot · pmic-rev3
curator design · lm95231-evb-rev1 · 96 spec · DS-LM95231 §6.2 · 88 sheet · TestInst · 74+3 more
▸ Reasoning · 3 steps
  1. VDDPLL needs same continuity treatment as the existing VDDD pair (DS §6.2).
  2. Tdelay 25 µs from Levels_CONT matches the rail's settle envelope (lm95231-evb-rev1 reuse).
  3. tfContinuity pattern fits; emit a new TestInst row + Limits row joined on TNum.
Reusing the continuity pattern from lm95231-evb-rev1 with the VDDPLL pin pair from DS-LM95231 §6.2.
Delta vs reused source
+ TestInst · tfVDDPLL_Cont row
+ Limits · TNum 100 / bin 1
~ Levels_CONT · VDDPLL Tdelay 25 µs
tfContinuity proc · 0 line changes
Pipeline
CurateDraft sheetsDraft VBACompileValidate
02PCB intelligenceIPC-2581 → circuit-json, with reuse

Your designs become first-class context — ingested, queryable, reusable.

Point doc-ingestion at a repo of .ipc / KiCad files. Each one becomes a typed PCBDesign with canonical circuit-json (the tscircuit shape). Components, nets, signal layers — all queryable rows the curator scores when the pilot reaches for a reference design.

  • Pilot emits circuit-json directly — no IR conversion, no DSN round-trip. The schematic viewer renders it inline.
  • Side-by-side compare at /pcb/compare?left=&right= with reused / removed / added / renumbered counts. "Highlight reused" toggle for review walk-throughs.
  • Reference parts library — ~15 high-frequency devices with pinouts the LLM consults. No hallucinated pin numbers on common parts.
  • Round-trip preserved — IPC-2581 source stored alongside the parsed circuit-json, downloadable as .circuit.json.
  • Reuse with refdes preservation — when a sub-circuit fits, the pilot copies it forward; refdes stays stable so BOM joins keep working.
Ingestion pipeline
IPC-2581
.ipc / KiCad
doc-ingestion
MCP · port 3003
PCBDesign
circuit-json + nets
Reference library
lm95231-evb-rev1
max15301-buck-2A
tps54360-3v3
ads1115-4ch-i2c
tlv9061-buf
lm358-x10
pca9555-gpio
ina260-12v
/pcb/compare · lm95231-evb · rev1 ↔ rev2
rev1
U1
rev2
U1
● 14 reused● 3 added● 1 removed[ Highlight reused ]
03STDF intelligenceV4 parser + 7 chat tools

The pilot proposes test-program edits against the actual lot data — not hypotheticals.

Drop in a .std or .std.gz lot. The STDF MCP parses V4 records natively (no Python or wasm at runtime) — MIR, PCR, PTR, TSR, HBR/SBR, PRR. Every analytical view the pilot can call sits behind a tool the LLM can reach for in-chat.

  • Seven chat tools the LLM calls in-flight — yield_summary, parametric (per-test mean/σ/Cp/Cpk), first_fail_pareto, test_time_pareto (TSR.TEST_TIM × EXEC_CNT primary + datalog-PTR fallback), wafer_map, limit_drift, correlate (cross-lot trend by TEST_NUM).
  • Yield-by-site + site→socket overlay — flag the outlier socket without spelunking.
  • First-failure pareto — distinct from "top failing tests": it counts which test FIRST killed each die. Top entry is the highest-leverage fix.
  • Wafer-map with cluster detection — edge / ring / single-quadrant heuristics; pair with physical intuition (probe alignment, CMP uniformity, thermal coupling).
  • Limits-vs-spec drift with relaxCandidate flag on tests ≥ 2σ inside the spec window. Quote the σ-headroom in the recommendation.
lot MXXXXXXSC2E9921 · 192 parts · 2 HW bins
Yield by site
S0
97%
S1
96%
S2
98%
S3
95%
S4
71%
S5
96%
S6
97%
S7
98%
⚠ Site 5 — investigate socket alignment
First-failure pareto
IDD_typical
46
VDDPLL_Cont
11
Continuity_Open
6
VCM_offset
3
The pilot calls these in-chat
stdf_get_yield_summary
stdf_get_parametric
stdf_get_first_fail_pareto
stdf_get_test_time_pareto
stdf_get_wafer_map
stdf_get_limit_drift
stdf_correlate
04Test-program intelligence287 KB entries · 23 VBA rules · 8 cross-sheet rules

IG-XL fluency that compiles — typed knowledge base, validated output, IG-Link in the loop.

IG-XL is its own language with its own conventions. ATE·IQ carries a typed knowledge base built against a real working programme — 287 VBT-API entries, each citing its UltraFLEX documentation page. The pilot doesn't reach for a public-internet LLM's guess at what TheHdw.DCVI.Pins(X).SpikeCheck does; it looks up the entry and the prohibition.

  • 287 typed VBT-API entries covering 14 instruments detected on a real digital programme. DCVI, DCVS, PPMU, Digital, UltraSource, UltraCapture, Patterns, Utility, DSSC, DIB, SyncPanel, MWReceiver, MWSource — each carrying identity, electrical envelope, settle times, prohibitions.
  • 23 VBA quality rules (R01–R23) across dev / prod profiles. Catches On-Error patterns, hardcoded GPIB addresses, per-pin loops, ActiveSites enumeration outside report formatting, Hungarian-prefix mismatches, blocking-timing primitives, missing PassFail writes.
  • 8 cross-sheet rules on every generation. Arg-ceiling (Arg60+ unusual), opcode allowlist, Flow → TestInst / Limits / Binning resolution, TestInst sheet-ref resolution, Pin Levels Tdelay sanity, tf* procedure-prefix convention.
  • Spec ingestion — Jama Connect API sync or drop a PDF datasheet. Section-indexed; citation-ready in chat. <cite kind="spec" id="<specId>#<reqId>"/> deep-links to the cited requirement.
  • .igxlproj schema in the system prompt — generator output isn't a guess at the project XML shape. The full 7-block schema with every required sub-field is embedded so IGLinkCL actually compiles the output.
  • Generation contract regression test — the reference programme's .igxlProj is the schema oracle. A future prompt edit that drops a mandatory block breaks the test loudly.
  • IG-Link CLI integration — compile runs are first-class artefacts. The Run viewer at /runs/[id] shows the diff, the Validation tab, the build log, all downloadable.
excel · pmic-test.xlsm · task pane
TestInst
Test NameTypeProcPin Levels
tfContinuityVBTtfContinuityLevels_CONT
tfScanChainVBTtfScanChainLevels_SCAN
tfIDDQVBTtfIDDQLevels_VT
tfVDDPLL_ContVBTtfContinuityLevels_CONT
Run summary
VBA quality · 23 rules · 0 errors
Cross-sheet · 8 rules · 0 failures
1 warning · Tdelay unit check
knowledge base
14 instruments detected · 287 entries · cited to source docs
/runs/[id] · run-detail
Artifacts9
Validation
Logs2
Valid · 0 failures, 1 warning
Flow
11
Flow.txt
TestInst
11
TestInst.txt
Limits
178
Limits.txt
Binning
4
Binning.txt
PinLevels
39
Levels.txt
Talk to us

Bring an .xlsm. Leave with a working IG-Link draft.

30-minute scoping call. We follow up with a quote within one business day.